signal cnt_reset : integer range 0 to 511 :=0;
count_reset : process(sysclk,cnt_reset)
begin
    if(sysclk'event and sysclk= '1')then
        if(reset = '1')then
            cnt_reset <= 0 ;
        elsif cnt_reset = 511 then
            cnt_reset <= 511;
        else
            cnt_reset <= cnt_reset + 1;
        end if;
    end if;
end process count_reset;

reset_done <= '1' when cnt_reset = 511 else '0';
RESET_n <= '0' when cnt_reset <= 240 esle '1';
-----------------------------------------------------

-- STC : state machine transition current
-- STN : state machine transition next

----------------------------------------------------
   Sda_T <= '0' when ((master_slave = '1' and arb_lost = '0' 
                       and sda_cout_reg = '0')
                       or (master_slave = '0' and slave_sda = '0')
                       or stop_scl_reg = '1') else
            '1';
----------------------------------------------------
-- parameter define above the arthitecture
ENTITY vga_timing_generator IS
  GENERIC (WIDTH       : integer := 1024;
           H_FP        : integer := 24;
           H_SYNC      : integer := 136;
           H_BP        : integer := 160;
           HEIGHT      : integer := 768;
           V_FP        : integer := 3;
           V_SYNC      : integer := 6;
           V_BP        : integer := 29;
           HEIGHT_BITS : integer := 10;
           WIDTH_BITS  : integer := 10;
           HCOUNT_BITS : integer := 11;
           VCOUNT_BITS : integer := 11;
           DATA_DELAY  : integer := 0


           );
  PORT (CLK            : IN  std_logic;
        RST            : IN  std_logic;
        HSYNC          : OUT std_logic;
        VSYNC          : OUT std_logic;
        X_COORD        : OUT std_logic_vector(WIDTH_BITS-1 DOWNTO 0);
        Y_COORD        : OUT std_logic_vector(HEIGHT_BITS-1 DOWNTO 0);
        PIXEL_COUNT    : OUT std_logic_vector(WIDTH_BITS+HEIGHT_BITS-1 DOWNTO 0);
        DATA_VALID     : OUT std_logic;
        DATA_VALID_EXT : OUT std_logic);
END vga_timing_generator;

-----------------------------------------------------
--conditional compiled in VHDL
-----------------------------------------------------
constant mycondition : boolean := true ;

entity myentity is 
	generic( C_myconditon : boolean)
	port(....)
	
P3: process
begin
	...stuff(sequential statemets)
	if C_myconditon then
		... stuff
	else
		... stuff
	end if;
	end process ps3;
	
genlabel: 
if <boolean expression> generate 
  <conditional compiled code> 
end generate;

---------------------------------------------------
---------------------------------------------------

package display is
type display_enum_t is (small, medium, large);
type display_spec_t is
record
PixelsPerLine : positive;
LinesPerFrame : positive;
end record display_spec_t;

type displays_t is array (display_enum_t) of display_spec_t;

constant example_spec : display_spec_t :=
(PixelsPerLine => 32,
LinesPerFrame => 16);

constant bag_o_specs :
displays_t := (
small => (
PixelsPerLine => 32,
LinesPerFrame => 16
),
medium => (
PixelsPerLine => 64,
LinesPerFrame => 32
),
large => (
PixelsPerLine => 1024,
LinesPerFrame => 512
)
);

constant test_this_line : positive := bag(large).PixelsPerLine;

end package display;
-------------------------------------------------------------------------------

------------------------------------------------------------------------------
